Networks for processing digital representations of analog signals require an analog to digital convertor (ADC) as an interface between the analog signal and the network. Typical ADCs are synchronized to a clock and include sample and hold circuitry for sampling the amplitude of an input analog signal at the beginning of each clock cycle and holding the sampled value for the duration of the conversion time. The conversion circuitry then generates an m-bit digital representation of the held, sampled amplitude. A flash converter generates this digital representation in one clock cycle.
Two types of errors are inherent in the above-described conversion system. The first type, quantization error, results from the division of the input dynamic range of the ADC into 2.sup.m quantized intervals. The accuracy of direct amplitude measurement is limited by the magnitude of the quantized interval. The second type of error, aliasing, results from sampling the input analog signal at fixed intervals. The ADC does not respond to variation of the input analog signal except during a given sampling interval. If the sampling rate is too slow, the digital representation includes an aliasing error and an accurate reconstruction of the input analog signal is impossible.
Most conversion systems include anti-aliasing hardware including filters to limit the bandwidth of the input analog signal. Additionally, a flash convertor for generating an m-bit representation requires 2.sup.m -1 comparator circuits. Thus, the above-described ADC system is hardware intensive.
Further, a generalized network concept utilizing a quantized analog input signal for modelling analog (within quantization noise limits), digital, or mixed analog/digital networks are being developed. One example of such a system is disclosed in the co-pending, commonly assigned patent application to Sloane entitled "GENERAL NETWORK MODELING AND SYNTHESIS" filed Dec. 15, 1988. This network may operate as an asynchronous system, and thus aliasing effects do not occur unless the input signal is sampled.
In view of the above, it is apparent that the aliasing effect inherent in a sampling type ADC system increases the hardware requirements of the system and limits the utility of the generated digital signal for modelling analog systems. Further, information regarding the variation of the input analog signal during a given clock cycle is lost. Accordingly, an ADC conversion system that does not sample the input analog signal would obviate these disadvantages.